The invention concerns: a synchronous digital channel cell assembly device, a synchronous digital channel cell disassembly device, a synchronous digital channel switching center including cell assembly and disassembly devices of this kind, and an asynchronous digital channel switching center for routing to other switching centers cells produced by a cell assembly device of this kind.
In a synchronous network the digital channels are conveyed by synchronous multiplex links at a bit rate of 2.048 Mbit/s, for example, organized into recurrent frames having a fixed frame period and divided into time slots of fixed duration. A sample of each synchronous channel is represented by a binary word placed in a time slot occupying a fixed position in the frame. In an asynchronous network logical channel binary data is conveyed by asynchronous transfer mode packets known as cells having a fixed length and including a header identifying the logical channel conveyed by the cell.
In the current state of the art synchronous telecommunication networks are clearly separated from asynchronous networks. When an asynchronous network needs to use conventional services available in a synchronous telecommunication network it uses a gateway between the two networks.
A gateway carries out cell assembly which consists in placing in a cell conveying a logical channel, binary words each representing one sample of a synchronous channel so that this data can be transmitted from the synchronous network to the asynchronous network. The gateway also carries out cell disassembly which consists in extracting from each cell received by the gateway binary words each corresponding to one sample of a synchronous channel and reconstructing a synchronous time-division multiplex link organized into recurrent frames having a fixed period, each frame being made up of time slots conveying respective different synchronous channels. The gateway places in these time slots the respective binary words corresponding to these synchronous channels.
In Europe, the synchronous digital channels are conveyed by 2.048 Mbit/s synchronous multiplex links organized into recurrent frames having a period of 125 microseconds. Each frame is divided into 32 time slots each conveying one octet corresponding to a 64 kbit/s channel. In the standard format each asynchronous transfer cell includes five header octets and 48 payload octets. The cell assembly device of a gateway could therefore assemble each cell by placing therein 48 octets representing 48 successive samples of the same synchronous channel. In fact, the cell assembly device used in a gateway of this kind places only two octets belonging to the same channel, for example, representing a cell assembly time of 0.25 ms. This is because CCITT Recommendation Q.551 places an upper limit of 1 ms on the round trip delay through a synchronous network. The cell assembly and disassembly device of a gateway of this kind thus causes a total delay of 0.5 ms. This conforms to the provisions of Recommendation Q.551 but is wasteful of resources as each cell includes 46 unused octets.
Asynchronous transfer mode switching centers have now reached a stage of development whereby it is feasible to use them as low-cost synchronous channel switching centers within synchronous networks. The very high bit rate of the asynchronous multiplex links processed by asynchronous switching networks makes it feasible to switch a very large number of synchronous channels with much less hardware than conventionally used in a synchronous channel switching center. The problem therefore arises of converting synchronous channels into asynchronous channels and of converting the asynchronous channels back into synchronous channels after switching. The prior art cell assembly device used in the type of gateway mentioned above is not suitable for this application because of the wasteful use of resources that the very low fill ratio of each cell produced by a cell assembly device of this kind represents.